Loading example design¶

Goal¶

In this tutorial, you will load example design into Kintex FPGA that’s part of Lion DPU.

Prerequisites¶

• Example design from Tutorial files

  • Tutorial bitstream: Tutorials/Lion/lion_dpu.bit

• AMD Vivado Lab Edition installed on EGSE Host

Steps EGSE Host¶

1. Upload example bitstream to EGSE Host

2. Verify the bitstream is uploaded

   customer@egse-host:~$ ls -lh lion_dpu.bit
   -rw-rw-r-- 1 customer customer 16M Feb 17 17:51 lion_dpu.bit
   

3. Power on the Lion

   customer@egse-host:~$ sml power on
   Powering on...Success
   

4. Power on the DPU part of Lion

   customer@egse-host:~$ sml dpu power on
   Powering on...Success
   

5. Start XSDB

   customer@egse-host:~$ xsdb
   rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't
   find it in the terminfo database. Expect some problems.
   
   ****** System Debugger (XSDB) v2024.2
   **** Build date : Oct 29 2024-10:16:47
       ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
       ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights  Reserved.
   
   
   xsdb% connect
   tcfchan#0
   xsdb% targets
   1  xcku035
   xsdb%
   

6. Lower JTAG frequency to maximum supported value

   xsdb% jtag targets 1
   xsdb% jtag frequency 1500000
   1500000
   

7. Load bitstream

   xsdb% fpga lion_dpu.bit
   100%   15MB   0.2MB/s  01:24
   

8. Start minicom to observe output of test application

   customer@egse-host:~$ minicom -D /dev/sml/lion-dpu-uart-1
   uart0
   uart0
   uart0
   

Summary¶

In this tutorial, you’ve loaded the example design using JTAG and observed output of test application. If you are interested in details of that design, please contact Smart Mission Lab support or KP Labs representative directly.